1. Field of the Invention
The present invention relates to a method for testing a memory device, and more particularly to a method for detecting a process defect of a memory device within a short period of time.
2. Description of the Prior Art
As generally known in the art, a memory device includes a memory bank for storing data, a row circuit unit and a column circuit unit for reading/writing data from/to the memory bank, and an input/output unit for inputting/outputting data.
From among these components, the memory bank including a plurality of memory cell arrays performs a very important function in the memory device. However, a leakage current may be introduced into an unspecific bit line of the memory band due to a process defect, so that cell fault may occur due to the leakage current.
Therefore, a manufacturer screens various failures in the memory bank through several steps and various methods.
As a result of the screen, when a cell having a defect is detected, the cell is replaced with a redundancy circuit.
A memory bank includes a plurality of memory cell blocks (see FIG. 1 for the construction of a memory bank), and the memory cell blocks are sequentially tested. That is, after the test for a first memory cell block has been finished, the test for a second memory cell block is performed. After the test for the second memory cell block has been finished, the test for a third memory cell block is performed. In such a manner, the test is sequentially performed until the test for the last memory cell block has been completed.
However, in order to test one word line through active, write, and precharge operations, several hundreds of μs to several ms may be required. Therefore, the conventional test method has a problem in that a very long test time is required to detect a weak cell.